FIG. 1 shows a conventional EEPROM cell 10 in which more than two binary states may be represented by programming cell 10's threshold voltage to one of many predetermined levels. When cell 10 is read, the current level conducted therein is dependent upon the threshold voltage thereof.
Cell 10 includes a storage transistor 12 and a select transistor 14 formed in a P- substrate 16. N+ diffusion region 18 serves as the source of storage transistor 12, N+ diffusion region 20 serves as the drain of storage transistor 12 as well as the source for select transistor 14, and N+ diffusion region 22 serves as the drain of select transistor 14. A bit line BL of an associated memory array (not shown) is coupled to drain 22 of select transistor 14. A high impedance resistor 32 is coupled between drain 22 of select transistor 14 and ground potential. A voltage sensing circuit 34 coupled to drain 22 measures the voltage at drain 22 to determine the threshold voltage V.sub.t, and thus the multiple-bit data stored in cell 10. Storage transistor 12 has a floating gate 24 and a control gate 26, and select transistor 14 has a select gate 28. A tunnel window (not shown) is formed within tunnel oxide 30 layer to facilitate electron tunneling between floating gate 24 and drain 20.
Floating gate 24 is charged by applying an erase voltage V.sub.e between 16-20 V to control gate 26 and 16-20 V to select gate 26 and 0 V is applied to bit line BL and source 18. Electrons tunnel from drain 20 to floating gate 24, thereby increasing the threshold voltage V.sub.t of storage transistor 12.
Cell 10 may be programmed by applying a program voltage V.sub.p between 13-20 V to bit line BL and select gate 28 while control gate 26 is grounded and source 18 is in a high impedance state. The resultant electric field causes electrons to tunnel from floating gate 24 to drain 20, thereby discharging floating gate 24 and decreasing the threshold voltage V.sub.t of cell 10. The resultant V.sub.t of storage transistor 12, and thus the current conducted by cell 10 during a read operation, may by controlled by adjusting the program voltage V.sub.p.
Accordingly, more than one bit of information may be stored in cell 10 by altering the threshold voltage V.sub.t of cell 10 to one of many possible values. Typically, the threshold voltage of cell 10 is approximately 0 V in its uncharged state and approximately -2 V and 4 V in its fully positive and negative charged states, respectively. The range of V.sub.t for multi-level applications is approximately 2.5 V. However, variations in the thickness of the tunneling oxide layer 30, as well as the coupling ratio between floating gate 24 and control gate 26, make it difficult to manipulate the threshold voltage V.sub.t of storage transistor 12. Moreover, cell 10 suffers from read disturb problems which may adversely affect the reliability of cell 10. Further, the relatively high voltages across the P/N junctions within cell 10 during erasing and programming undesirably limit the extent to which the size of cell 10 may be reduced.
It would thus be desirable for a flash EEPROM cell in which the threshold voltage V.sub.t may be controlled independently of process variations. It would be desirable for a flash EEPROM cell that not only uses low programming and erasing voltages but also is immune from read disturb problems.